A Flexible Hybrid Transactional Memory Multicore on FPGA
نویسندگان
چکیده
In this paper we present the design and implementation of an MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.
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تاریخ انتشار 2011